Figure 4: Feedback Region for Front Wire Discrepancy 3 Atpg 3.1 Simulator 3.2 Generator Generating Test Patterns for Bridge Faults in Cmos Ics

References 1] M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers , C-34:658{663, 1985. 2] J. M. Acken and S. D. Millman. Accurate mod-eling and simulation of bridging faults. In Pro-Campbell. Double-bridge test structure for the evaluation of type, size and density of spot defects. foreach feedback bridge fault (FBF) front wire unfaulted value = 0, fault block output = 1 if test generation is successful (sequential behavior must be prevented) F BF is covered, move to the next fault else front wire unfaulted value = 1, fault block output = 0 if test generation is successful (sequential behavior must be prevented) F BF is covered, move to the next fault else if F BF is a feedback fault with no fanout F BF is undetectable, move to the next fault else back wire unfaulted value = 0, fault block output = 1 if test generation is successful (oscillation must be prevented) F BF is covered, move to the next fault else back wire unfaulted value = 1, fault block output = 0 if test generation is successful (oscillation must be prevented) F BF is covered, move to the next fault else F BF is undetectable Figure 5: Pseudo-code for ATPG for bridge faults that may induce feedback Table 3: Breakdown of circuit bridge fault statistics number of PBFs is small compared to the number of faults, and in fact, only 309 diierent PBFs were used in the entire MCNC implementations of the ISCAS-85 benchmarks. We can see that the number of feedback bridge faults is a signiicant percentage of the number of bridge faults, and we could not expect to achieve useful fault coverage if we did not produce accurate tests for the feedback bridge faults. The number of feedback bridge faults with no fanout are important, because Lemma 1 says that they can only be detected with the discrepancy placed on the front wire. This means that there are a signiicant number of faults that can never be tested with the discrepancy placed on the back wire. Table 4 shows the number of bridge faults covered, proved untestable, or aborted by our system. For the ten circuits, we cover an average of 99.39% of the faults. We fail to generate tests for or prove untestable very few of the faults. Table 4 also shows the …